Trenched isolation regions are commonly utilized for electrically isolating adjacent structures in highly integrated semiconductor constructions. A common form of trenched isolation region is a so-called shallow trench isolation (STI) region.
The trenched isolation regions can be utilized, for example, for providing isolation between adjacent transistor structures. A difficulty which can occur when utilizing a trenched isolation region adjacent a transistor structure is that a sharp active corner at the trenched isolation region edge can lead to a high fringing electric field, which can establish a parasitic transistor with a lower threshold voltage (Vt) along the trench edge in parallel to the normal transistor. An edge transistor with a lower Vt provides a leakage path even before the normal transistor is turned “on.” This can lead to numerous problems during operation of the transistor, and can manifest as a “double hump” in the sub-threshold characteristics of the transistor.
Another problem that can occur with field oxide is thinning of the field oxide at corners under transistor gates. The thinning can occur due to thermal oxide tending to not grow as thick on the corners as in the central region of the field oxide. The thinning of the field oxide at the corners can exacerbate the fringing electric field problems discussed above, and can lead to decreased reliability of the oxide.
Numerous approaches have been developed for attempting to alleviate problems associated with sharp active corners at trenched isolation region edges, but such approaches have not yet proven to be fully satisfactory. Accordingly, it would be desirable to develop new methodologies for alleviating problems associated with sharp active corners at trenched isolation region edges.